With ongoing miniaturization, conventional silicon microelectronics will reach its limits. In a field-effect transistor, continued miniaturization will lead to an increase in disruptive short-channel effects, which restrict the performance of the field-effect transistor. In addition to the problems which arise with a single component, in a memory array there are also limits on the extent to which the storage medium can be scaled, for example the capacitance in a DRAM (dynamic random access memory) cannot be scaled to any desired extent.
The use of carbon nanotubes is under discussion as a possible successor technology to silicon microelectronics. Basic principles of carbon nanotubes are described, for example, in [1]. It is known that carbon nanotubes (depending on the tube parameters) have an electrical conductivity which ranges from semiconducting to metallic.
It is known from [2] to introduce a via hole into a gate electrode layer and to grow a vertical nanoelement in this via hole. This results in a vertical field-effect transistor with the nanoelement as channel region, it being possible to control the electrical conductivity of the channel region by means of the gate electrode region, which surrounds the nanoelement over approximately its entire longitudinal extent.
[3] has disclosed a field-effect transistor having a carbon nanotube as channel region, which is applied horizontally to a substrate. At two end portions, the carbon nanotube is coupled to a first source/drain region and a second source/drain region, respectively. A gate-insulating layer is applied to the carbon nanotube. An electrically conductive gate region is applied to the gate-insulating layer in a region between the two source/drain regions, it being possible to control the conductivity of the carbon nanotube by applying an electric voltage to the gate region. The carbon nanotube which has been applied horizontally in accordance with [3] means that a field-effect transistor of this type takes up a large amount of space, which runs contrary to the trend toward miniaturization.
Furthermore, it is known from the prior art to use what is known as an EEPROM (electrically erasable programmable read-only memory) memory cell or a flash memory cell as the permanent memory; in these memory cells, the stored information is coded in electrical charge carriers stored in a floating gate or in a charged storage layer. Information contained in the electrically conductive floating gate or in the electrically insulating charge storage layer (trapping layer) can be read by shifting the threshold voltage of the memory transistor.
However, the known EEPROM or flash memory cells have the problem that disruptive short-channel effects occur in the transistors involved with continued miniaturization.
[4] discloses an electronic component formed from electrically conductive first nanowires, a layer system applied to the first nanowires, and second nanowires applied to the layer system, the first and second nanowires being arranged at an angle to one another. Charge carriers generated by the nanowires can be stored in the layer system.
[5], [6] each disclose a memory cell comprising a silicon substrate as gate region, a silicon oxide layer formed on the silicon substrate and a nanotube formed thereon, it being possible for charge carriers to be introduced into the silicon oxide layer.
[7] discloses a vertical nanodimensional transistor using carbon nanotubes, and a method for fabricating a transistor of this type.
[8] discloses a field-effect transistor having a first nanotube and a second nanotube, the first nanotube forming a source region, a channel region and a drain region, and the second nanotube forming a gate region.
[9] discloses carbon nanotubes, the hollow cores of which are filled with a conductive filling material.
[10] discloses a system and a method for fabricating logic devices having carbon nanotube transistors.